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| Ordering number : ENA0432A LC87F06J2A Overview CMOS IC FROM 192K byte, RAM 8192 byte on-chip 8-bit 1-chip Microcontroller The SANYO LC87F06J2A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 66.6ns, integrate on a single chip a number of hardware features such as 192K-byte flash ROM (onboard rewritable), 8K-byte RAM, Onchip debugging function, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer with a prescaler (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two synchronous SIO ports, two UART ports (full duplex), four 12-bit PWM channels, VPS/PDC/PAL-WSS * XDS * EPG-J * VBID(Video-ID) Data-slicer, an universal remote control transmitter, an 8-bit 16-channel AD converter, a high-speed clock counter, a system clock frequency divider, and a 36-source 10-vector interrupt, ROM correction function feature. Features Flash ROM * Single 5V power supply, on-board writeable * Block erase in 128 byte units * 196608 x 8 bits (LC87F06J2A) RAM * 8192 x 9 bits Bus Cycle Time * 66.6ns (15MHz, 1/1 frequency division ratio ) Note: Bus cycle time indicates the speed to read ROM. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. Ver.1.003 31407HKIM 20070115-S00002 No.A0432-1/32 LC87F06J2A Minimum Instruction Cycle Time (tCYC) * 200ns (15MHz, 1/1 frequency division ratio) Ports * Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units: 75 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PB0 to PB2, PCn, S2Pn, XT2, PWM0, PWM1, PEn, PFn ) Ports whose I/O direction can be designated in 4 bit units: 8 (P0n) * Normal withstand voltage input ports: 1 (XT1) * Dedicated oscillator ports: 2 (CF1, CF2) * Reset pin: 1 (RES) * Data slicer pins: 2 (PB4, PB6) * Power pins: 11 (VSS1 to VSS4, VDD1 to VDD4, VSSVCO, VDDVCO, VDDODA) Timer * Timer 0: 16-bit timer/counter with capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) * Timer 1: 16-bit timer/counter that support PWM/ toggle output Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Timer 8: 16-bit timer with a prescaler (may be divided into 8-bit timers) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillator), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. Day and Time Counter 1) Using with a base timer, it can be used as 65,000 days + minute + second counter. High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real time. SIO * SIO 0: 8 bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits) * SIO 1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) Continued on next page. No.A0432-2/32 LC87F06J2A Continued from preceding page. * SIO2: 8 bit synchronous serial interface 1) LSB first mode 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 32 bytes) * SIO 7: 8 bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) * SIO 8: 8 bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) UART: 2 channels 1) Full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC) AD Converter * 8 bits x 16 channels PWM * Multifrequency 12-bit PWM x 4 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, T0IN and TOHCP) 1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) 2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. Small Signal Detect Function 1) Small Signal Detect Function is available in the following two terminals. P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1/SSGI0 P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1/SSGI1 2) Capable of detecting a pulse with certain level of amplitude. 3) Input bias circuit available. H-Counter 1) H-counter can choose one of the following signals as count-clock. HCTR signal of P22/INT4/T1IN/T0LCP/T0HCP/HCTR terminal CSYNC signal of PB6/CVD/CSYNC terminal Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form PB6/CVD/CSYNC terminal 2) Counter 7bit (up) + 1bit (over-flow flag) Field (first/second) Detect Function 1) Distinguishes a field with one of the following signals. CSYNC signal of PB6/CVD/CSYNC terminal Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form PB6/CVD/CSYNC terminal 2) Outputs Field-Detect signal from PB0/DS1FLD terminal Watchdog Timer 1) External RC watchdog timer 2) Interrupt and reset signals selectable No.A0432-3/32 LC87F06J2A Data-Slicer * XDS 1) Supports XDS-1X and XDS-2X (With auto-recognition) * VPS/PDC/PAL-WSS Data-slicer can choose one of the following three formats to the TV Line(VBI). 1) PDC/UDT and other Teletext data 2) VPS 3) PAL-WSS * VPS * EPG-J * Antiope * VBID(VideoID) Universal Remote Control Transmitter Circuit * Outputs remote control signal from PF4/IRP terminal. Interrupts * 36 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/Base timer0/Base timer1/Remocon transmit T0H/INT6/SIO7 T1L/T1H/INT7/SIO8 SIO0/UART1 receive/UART2 receive/T8L/T8H SIO1/SIO2/UART1 transmit/UART2 transmit ADC/T6/T7/PWM4, PWM5/ Automatic transmission Port 0/T4/T5/Data slicer /PWM0, PWM1 Interrupt signal * Priority Level: X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels * 4096 levels maximum (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation Circuits * RC oscillator circuit (internal): For system clock * CF oscillator circuit: For system clock with internal Rf * Crystal oscillator circuit: For low-speed system clock * Multifrequency RC oscillator circuit (internal): For system clock No.A0432-4/32 LC87F06J2A System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by system reset or occurrence of interrupt. * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the Reset pin to the lower level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and the Day-and-time counter. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the Reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port 0. (4) Having an interrupt source established in the base timer circuit. Onchip Debugging * Permits software debugging with the test device installed on the target board. ROM Correction Function * PC match address registers: 4 * Ram for ROM correction: 128byte Package Form * QIP100E(14x20): "Lead-free type" Development Tools * On-chip debugger: TCB87 TypeA + LC87F06J2A : TCB87 TypeB + LC87F06J2A Flash ROM Programming Boards Package QIP100E(14x20) Programming boards W87F05256Q Flash ROM Programmer Maker Flash Support Group, Inc. (Single) Flash Support Group, Inc. (Gang) Model AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) AF9723(Main body) (including product of Ando Electric Co.,Ltd) AF9833(Unit) (including product of Ando Electric Co.,Ltd) SANYO SKK(Sanyo FWS) Application Version: After 1.03 Chip Data Version: After 2.01 LC87F06J2 Revision: After 01.86 Revision: After 02.04 LC87F06J2A FAST Supported version Revision: After 02.61 Device LC87F06J2A FAST No.A0432-5/32 LC87F06J2A Package Dimensions unit : mm (typ) 3151A 23.2 80 81 51 50 0.8 14.0 20.0 100 1 0.65 (0.58) (2.7) 31 30 0.3 0.15 3.0max 0.1 SANYO : QIP100E(14X20) 17.2 No.A0432-6/32 PC6/DBGP1 PC7/DBGP2 PC3/AN10 PC4/AN11 PC5/DGBP0 PA0/SO7 PC1/AN8 PC2/AN9 PB6/CVD/CSYNC PC0/OCSYNC PB4/FILTSLC PB0/DS1FLD PA1/SI7/SB7 PB1 PB2 VSSVCO VDDVCO VDD3 VSS3 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PA2/SCK7 100 1 Pin Assignment PA3/SO8 VDDODA P36 P35/URX2 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP 2 PA4/SI8/SB8 3 PA5/SCK8 4 P70/INT0/T0LCP 5 P71/INT1/T0HCP 6 P72/INT2/T0IN/T0LCP 7 8 P73/INT3/T0IN/T0HCP RES 9 XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ 31 32 P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1/SSGI1 P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP/HCTR P21/INT4/T1IN/T0LCP/T0HCP P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1/SSGI0 P07/T7O P06/T6O P05/CKO P04 P03 P02 P01 P00 VSS2 VDD2 PWM0 PWM1 SI2P3/SCK2O SI2P2/SCK2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LC87F06J2A LC87F06J2A 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Top view PE0/AN12 PE1/AN13 PF0 PF1 PF2 PF3 PF5 PF6 PF7 PE4 PE5 PE6 PE7 VSS4 VDD4 PF4/IRP PE2/AN14 PE3/AN15 SI2P0/SO2 SI2P1/SI2/SB2 SANYO: QIP100E(14x20) "Lead-free Type" No.A0432-7/32 LC87F06J2A System Block Diagram IR PLA Interrupt Control Flash ROM Standby Control CF RC Xtal MRC SIO0 Bus Interface ACC Clock Generator PC SIO1 Port 0 B Register SIO2 Port 1 C Register SIO7 SIO8 Port 3 ALU Port 7 Timer 0 ADC PSW Timer 1 INT0-7 Port 2 (Small signal detect) Port A RAR Timer 4 RAM Timer 5 Stack Pointer Timer 6 Port B Watchdog Timer Timer 7 Port C Onchip Debugger Timer 8 Port E UART1 Port F UART2 PWM4, 5 PWM0,1 Port 8 H-counter Base timer Data slicer Date slicer RAM Universal remote control transmitter Day and time counter No.A0432-8/32 LC87F06J2A Pin Description Pin Name VSS1, VSS2 VSS3, VSS4 VSSVCO VDD1, VDD2 VDD3, VDD4 VDDVCO, VDDODA Port 0 P00 to P07 I/O * 8-bit I/O port * I/O specifiable in 4-bit units * Pull-up resistor can be turned on and off in 4-bit units * HOLD release input * Port 0 interrupt input * Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output Port 1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P10: SIO0 data output P11: SIO0 data input, bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input, bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output, Beeper output Port 2 P20 to P27 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT6 input/timer 0L capture 1 input/small signal input P21, P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P22: NT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/HCTR signal input P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT7 input/timer 0H capture 1 input/small signal input P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ Timer 0H capture input * Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising/ Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes Yes I/O Power supply pin (-) Function description Option No - Power supply pin (+) No Port 3 P30 to P36 I/O * 7-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P30: PWM4 output P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive Yes Continued on next page. No.A0432-9/32 LC87F06J2A Continued from preceding page. Pin Name Port 7 P70 to P73 I/O I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer P71: INT1 input/HOLD release input/Timer 0H capture input P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input * Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Function description Option No Port 8 P80 to P87 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Other functions P80-P87: AD converter input port No Port A PA0 to PA5 I/O * 6-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions PA0: SIO7 data output PA1: SIO7 data input, bus I/O PA2: SIO7 clock I/O PA3: SIO8 data output PA4: SIO8 data input, bus I/O PA5: SIO8 clock I/O Yes Port B PB0 to PB2 PB4, PB6 I/O * 5-bit I/O port * I/O specifiable in 1-bit units * Other functions PB0: Output for field recognition signal PB4: LPF connection for Slicer PLL PB6: Input for CSYNC signal/CVD (Composite Video) signal Yes Port C PC0 to PC7 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Other functions PC0: OCSYNC output PC1 to PC4: AD converter input port PC5 to PC7: On-chip Debugger Yes Port E PE0 to PE7 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Other functions PE0-PE3: AD converter input port No Port F PF0 to PF7 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Other functions PF4: Remote control signal output No Continued on next page. No.A0432-10/32 LC87F06J2A Continued from preceding page. Pin Name SIO2 Port SI2P0 to SI2P3 I/O I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Other functions: SI2P0: SIO2 data output SI2P1: SIO2 data input, bus input/output SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0 PWM1 RES XT1 O O I I * PWM0 output port * General-purpose I/O available * PWM1 output port * General-purpose I/O available Reset pin * Input terminal for 32.768kHz X'tal oscillation * Other functions: General-purpose input port XT2 I/O Must be connected to VDD1 if not to be used. * Output terminal for 32.768kHz X'tal oscillation * Other functions: General-purpose I/O port Must be set for oscillation and kept open if not to be used. CF1 CF2 I O Ceramic resonator input pin Ceramic resonator output pin No No No No No No No Function description Option No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port P00 to P07 Options selected in units of 1 bit Option type 1 2 P10 to P17 P20 to P27 P30 to P36 PA0 to PA5 PC0 to PC7 PB0 to PB2 PB4, PB6 PE0 to PE7 PF0 to PF7 P70 P71 to P73 P80 to P87 SI2P0, SI2P2 SI2P3 PWM0, PWM1 SI2P1 No CMOS (when selected as ordinary port) N-channel open drain (when SIO2 data is selected) XT1 XT2 No No Input only Output for 32.768kHz crystal oscillator N-channel open drain (when in general-purpose output mode) No No No No No No No N-channel open drain CMOS N-channel open drain CMOS Programmable Programmable No No 1 bit 1 2 No CMOS N-channel open drain CMOS No No Programmable 1 bit 1 2 CMOS N-channel open drain CMOS N-channel open drain Output type Pull-up resistor Programmable (Note 1) No Programmable Programmable Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to P03, P04 to P07). No.A0432-11/32 LC87F06J2A Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 =VSS4=VSSVCO= 0V Parameter Maximum Supply voltage Input voltage Input/Output Voltage VI(1) VIO(1) Symbol VDDMAX Pins/Remarks VDD1, VDD2, VDD3, VDD4, VDDVCO, VDDODA XT1, CF1, RES Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1, XT2 Peak output current IOPH(2) IOPH(3) Average output current (Note 1-1) IOMH(2) High level output current IOMH(3) Total output current IOAH(3) IOAH(4) IOAH(1) IOAH(2) IOMH(1) IOPH(1) Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 P71 to P73 Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 P71 to P73 P71 to P73 PWM0, PWM1 SI2P0 to SI2P3 Ports 0, 2, 3 Port 0, 2, 3 PWM0, PWM1 SI2P0 to SI2P3 IOAH(5) IOAH(6) IOAH(7) IOAH(8) IOAH(9) IOAH(10) IOAH(11) Peak output current IOPL(1) PB0 to PB2 Ports A, C Ports A, C, PB0 to PB2 Port F Ports 1, E Ports 1, E, F PB4, PB6 P02 to P07 Ports 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 Low level output current PWM0, PWM1 IOPL(2) IOPL(3) Average output current (Note 1-1) IOML(1) P00, P01 Ports 7, 8, XT2 P02 to P07 Ports 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 IOML(2) IOML(3) P00, P01 Ports 7, 8, XT2 Per 1 application pin. Per 1 application pin. 20 7.5 15 Per 1 application pin. Per 1 application pin. Per 1 application pin. 30 10 20 Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 application pin. Total of all applicable pins Total of all applicable pins Total of all applicable pins -20 -20 mA -40 -20 -20 -40 -20 Total of all applicable pins Total of all applicable pins -50 Per 1 application pin. Per 1 application pin. Total of all applicable pins Total of all applicable pins -15 -3 -5 -20 -30 Per 1 application pin. Per 1 application pin. CMOS output select per 1 application pin -10 -20 -5 CMOS output select per 1 application pin -10 -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3=VDD4 =VDDVCO =VDDODA -0.3 VDD+0.3 V min -0.3 Specification typ max +6.5 unit Note 1-1: Average output current is average of current in 100ms interval. Continued on next page. No.A0432-12/32 LC87F06J2A Continued from preceding page. Specification Parameter Total output current Symbol IOAL(1) IOAL(2) IOAL(3) IOAL(4) Low level output current IOAL(5) IOAL(6) Pins/Remarks Port 7, XT2 Port 8 Ports 7, 8, XT2 PWM0, PWM1 SI2P0 to SI2P3 Ports 0, 2, 3 Ports 0, 2, 3 PWM0, PWM1 SI2P0 to SI2P3 IOAL(7) IOAL(8) IOAL(9) IOAL(10) IOAL(11) IOAL(12) IOAL(13) Maximum power consumption Operating temperature range Storage temperature range Tstg Topr -20 -55 Pd max PB0 to PB2 Ports A, C Ports A, C PB0 to PB2 Port F Ports 1, E Ports 1, E, F PB4, PB6 QIP100E(14x20) Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins 40 40 80 40 70 110 40 523 70 C 125 mW Total of all applicable pins Total of all applicable pins 120 mA Conditions VDD[V] Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins min typ max 15 15 30 40 80 unit Recommended Operating Range at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter Operating supply voltage (Note 2-1, 2-2) Data-slicer Operating supply voltage Base timer Day and time counter Operating supply voltage Memory sustaining supply voltage High level input voltage VIH(1) Ports 1, 2, 3, A PB6 SI2P0 to SI2P3 P71 to P73 P70 port input /interrupt side VIH(2) Ports 0, 8 PB0 to PB2, PB4 Ports C, E, F PWM0, PWM1 VIH(3) VIH(4) VIH(5) P70 Watchdog timer side XT1, XT2, CF1, RES P20, P24 Small signal input side 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0.9VDD 0.75VDD 0.75VDD VDD VDD VDD 2.7 to 5.5 0.3VDD +0.7 VDD 2.7 to 5.5 0.3VDD +0.7 VDD V VHD VDD1 RAM and register contents in HOLD mode. 2.0 5.5 VDD(3) VDD(2) Symbol VDD(1) Pins/Remarks VDD1=VDD2 =VDD3=VDD4 =VDDVCO=VDDODA VDD1=VDD2 =VDD3=VDD4 =VDDVCO=VDDODA VDD1 * X'tal HOLD mode * Base timer clock is subclock. * FsX'tal=32.768kHz by crystal oscillation mode. 2.0 5.5 Conditions VDD[V] 0.196s tCYC 200s 1.47s tCYC 200s 0.196s tCYC 0.340s 4.75 5.25 min 4.5 2.7 Specification typ max 5.5 5.5 unit Note 2-1: VDD must be held greater than or equal to 4.5V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. No.A0432-13/32 LC87F06J2A Continued from preceding page. Parameter Low level input voltage Symbol VIL(1) Pins/Remarks Ports 1, 2, 3,A PB6 SI2P0 to SI2P3 P71 to P73 P70 port input /interrupt VIL(2) Ports 0, 8 PB0 to PB2, PB4 Ports C, E, F PWM0,PWM1 VIL(3) VIL(4) VIL(5) Composite video signal input voltage (Note 2-4) Instruction cycle time (Note 2-2) Oscillation frequency Range (Note 2-3) FmRC FmMRC FsX'tal XT1, XT2 FmCF(1) CF1, CF2 15MHz ceramic oscillation See Fig. 1. Internal RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal oscillation. See Fig. 2. tCYC Data-slicer Operating mode 4.75 to 5.25 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0.3 0.196 0.196 1.470 15 1.0 16 32.768 kHz 2.0 MHz 0.340 200 200 s VCVD(1) VCVD(2) Port 70 Watchdog Timer XT1, XT2, CF1, RES P20, P24 Small signal input side PB6(CVD) 2Vp-p input mode 1Vp-p input mode 5.0 0.7 1 1.3 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 5.0 VSS VSS VSS 1.4 2.0 0.8VDD -1.0 0.25VDD 0.25VDD 2.6 Vp-p 2.7 to 5.5 VSS 0.15VDD +0.4 V 2.7 to 5.5 VSS 0.1VDD +0.4 Conditions VDD[V] min Specification typ max unit Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: When setting DSLDACT register's bit7 = 0, bit6 = 0. See diagram 9 for external circuit. No.A0432-14/32 LC87F06J2A Electrical Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter High level input current Symbol IIH(1) Pins/Remarks Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C, E, F SI2P0 to SI2P3 RES PWM0, PWM1 IIH(2) IIH(3) IIH(4) Low level input current IIL(1) XT1, XT2 CF1 P20, P24 Small signal input side Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C, E, F SI2P0 to SI2P3 RES PWM0, PWM1 IIL(2) IIL(3) IIL(4) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) Low level output voltage VOL(1) VOL(2) XT1, XT2 CF1 P20, P24 Small signal input side Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 Ports 71, 72, 73 PWM0, PWM1 P30, P31(PWM4, 5 output mode) Ports 0, 1, 2, 3 Ports A, B, C, E, F SI2P0 to SI2P3 PWM0, PWM1, VOL(3) VOL(4) VOL(5) Pull-up resistation Rpu(1) Rpu(2) Hysteresis Voltage VHYS(1) Ports 7, 8, XT2 Ports 0, 1, 2, 3 Port 7 Ports A, C, E, F RES Ports 1, 2, 3, 7, A PB6 SI2P0 to SI2P3 VHYS(2) Pin capacitance CP P20, P24 Small signal input side All pins * For pins other than that under test: VIN=VSS * f=1MHz * Ta=25C Input voltage sensitivity Bias Voltage Composite video signal input clamping voltage VBIAS VCLMP Vsen P20, P24 Small signal input side P20, P24 Small signal input side PB6(CVD) Pedestal voltage 5.0 1.9 V 4.5 to 5.5 5.0 0.12VDD 0.5VDD Vp-p V 2.7 to 5.5 10 pF 4.5 to 5.5 0.1VDD 4.5 to 5.5 0.1VDD V 2.7 to 5.5 15 40 150 P00, P01 IOL=30mA IOL=5.0mA IOL=1.6mA VOH=0.9VDD 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 15 40 1.5 0.4 0.4 70 k IOL=10mA IOL=1.6mA 3.0 to 5.5 0.4 IOH=-0.4mA IOH=-10mA IOH=-1.6mA Using as an input port VIN=VSS VIN=VSS VIN=VBIAS+0.5 (VBIAS is bias voltage) IOH=-1.0mA IOH=-0.4mA 2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 -1 -15 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 1.5 V -8.5 -4.2 Using as an input port VIN=VDD VIN=VDD VIN=VBIAS+0.5 (VBIAS is bias voltage) Output disable Pull-up resistor OFF VIN=VSS (including the off-leak current of the output Tr.) 2.7 to 5.5 -1 2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 4.2 8.5 1 15 15 A Conditions VDD[V] Output disable Pull-up resistor OFF VIN=VDD (including the off-leak current of the output Tr.) 2.7 to 5.5 1 min Specification typ max unit No.A0432-15/32 LC87F06J2A Serial I/O Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width tSCKHA(1a) * Continuous data transmission/reception mode * SIO2 is not in use Input clock simultaneous. * Universal remote control transmitter is not in use simultaneous. * See Fig. 6. * (Note 4-1-2) tSCKHA(1b) * Continuous data transmission/reception mode * SIO2 is in use simultaneous. * Universal remote control transmitter is in use simultaneous. Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level pulse idth High level pulse idth tSCKHA(2a) * Continuous data transmission/reception mode * SIO2 is not in use Output clock simultaneous. * Universal remote control transmitter is not in use simultaneous. * CMOS output selected. * See Fig. 6.e tSCKHA(2b) * Continuous data transmission/reception mode * SIO2 is in use simultaneous. * Universal remote control transmitter is in use simultaneous. * CMOS output selected. * See Fig. 6. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold Time thDI(1) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.7 to 5.5 0.03 0.03 s tSCKH(2) +2tCYC tSCKH(2) +(25/3)tCYC tCYC 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3)tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected. * See Fig. 6. 4/3 1/2 tSCK 1/2 9 2.7 to 5.5 tCYC 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pins/ Remarks SCK0(P12) Conditions VDD[V] * See Fig. 6. min 2 1 1 Specification typ max unit Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page. No.A0432-16/32 LC87F06J2A Continued from preceding page. Parameter Output delay Input clock time tdDO(2) Symbol tdDO(1) Pins/ Remarks SO0(P10), SB0(P11) Conditions VDD[V] * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode. * (Note 4-1-3) 2.7 to 5.5 Output clock tdDO(3) * (Note 4-1-3) (1/3)tCYC +0.05 min Specification typ max (1/3)tCYC +0.05 1tCYC +0.05 s unit Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P14), SB1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.7 to 5.5 0.03 Output delay time Serial output tdDO(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.7 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected. * See Fig. 6. 2.7 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pins/ Remarks SCK1(P15) Conditions VDD[V] * See Fig. 6. min 2 2.7 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max uni Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock Serial output No.A0432-17/32 LC87F06J2A 3. SIO2 Serial I/O Characteristics (Note 4-3-1) Parameter Frequency Low level pulse width High level Pulse width tSCKHA(5a) * Continuous data transmission/reception mode of SIO0 is not in use simultaneous. Input clock * Universal remote control transmitter is not in use simultaneous. * See Fig. 6. * (Note 4-3-2) tSCKHA(5b) * Continuous data transmission/reception mode of SIO0 is in use simultaneous. * Universal remote control transmitter is in use simultaneous. Serial clock * See Fig. 6. * (Note 4-3-2) Frequency Low level pulse width High level pulse width tSCKH(6) tSCKHA(6a) tSCK(6) tSCKL(6) SCK2 (SI2P2), SCK2O (SI2P3) * Continuous data transmission/reception mode of SIO0 is not in use simultaneous. * Universal remote control Output clock transmitter is not in use simultaneous. * CMOS output selected. * See Fig. 6. tSCKHA(6b) * Continuous data transmission/reception mode of SIO0 is in use simultaneous. * Universal remote control transmitter is in use simultaneous. * CMOS output elected. * See Fig. 6. Data setup time Serial input tsDI(3) SI2(SI2P1), SB2(SI2P1) Data hold time thDI(3) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.7 to 5.5 0.03 Output delay time Serial output tdDO(5) SO2(SI2P0) SB2(SI2P1) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.7 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC tCYC 2.7 to 5.5 tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC * CMOS output selected. * See Fig. 6. 1/2 1/2 tSCK 4/3 10 2.7to 5.5 tCYC 4 tSCKH(5) Symbol tSCK(5) tSCKL(5) Pins/ Remarks SCK2 (SI2P2) 1 1 Conditions VDD[V] * See Fig. 6. min 2 Specification typ max unit Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. No.A0432-18/32 LC87F06J2A 4. SIO7, SIO8 Serial I/O Characteristics (Note 4-4-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width tSCKHA(8) Data setup time Serial input tsDI(4) SI7(PA1), SB7(PA1), SI8(PA4), Data hold time thDI(4) SB8(PA4) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.7 to 5.5 0.03 Output delay Input clock time tdDO(6) SO7(PA0), SB7(PA1), SO8(PA3), SB8(PA4) tdDO(7) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output Output clock mode. * See Fig. 6. 2.7 to 5.5 (1/3)tCYC +0.05 1tCYC +0.05 s 0.03 tSCKH(8) tSCK(8) tSCKL(8) 2.7 to 5.5 1/2 1.5 tSCK SCK7(PA2), SCK8(PA5) * CMOS output selected. * See Fig. 6. tSCKH(7) Symbol tSCK(7) tSCKL(7) Pins/ Remarks SCK7(PA2), SCK8(PA5) Conditions VDD[V] * See Fig. 6. * (Note 4-4-2) 2.7 to 5.5 min 2 1 tCYC 1 4/3 1/2 Specification typ max uni Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: When starting transmission/reception of SIO7(SIO8) using serial-clock-input, a time from SI7RUN(SI8RUN) being set when serial clock is "H" to the first negative edge of the serial clock must be longer than 1tCYC. Serial output Serial clock No.A0432-19/32 LC87F06J2A Pulse Input Conditions at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/1. INT3(P73) (The noise rejection clock is selected to 1/32.) tPIH(4) tPIL(4) INT3(P73) (The noise rejection clock is selected to 1/128.) tPIH(5) tPIL(5) tPIL(6) HCTR(P22) CSYNC(PB6) RES * Count clock inputs for H-counter are enabled. Reset acceptable 2.7 to 5.5 2.7 to 5.5 1 200 s * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 2.7 to 5.5 256 * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 2.7 to 5.5 64 2.7 to 5.5 2 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 min Specification typ max unit AD Converter Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter Resolution Absolute precision Conversion time TCAD N ET Symbol Pins/Remarks AN0(P80) to AN7(P87), AN8(PC1), AN9(PC2), AN10(PC3), AN11(PC4), AN12(PE0), AN13(PE1), AN14(PE2), AN15(PE3) AD conversion time=64 x tCYC (when ADCR2=1) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (Note 6-2) 4.5 to 5.5 3.0 to 5.5 AD conversion time=32 x tCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 12.54 (tCYC= 0.396s) 47.04 (tCYC= 1.47s) 12.54 (tCYC= 0.198s) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) VDD 1 V s max unit bit LSB A Note 6-1: The quantization error (1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register. No.A0432-20/32 LC87F06J2A Consumption Current Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 =VDDODA =VDDVCO Conditions VDD[V] * FmCF=15MHz ceramic oscillation mode * FsX'tal=32.768kHz by crystal oscillation mode * System clock set to 15MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. * Slicer PLL is in running. * Slicer RC oscillation is in running. * Data Slicer is in running. IDDOP(2) * FmCF=15MHz ceramic oscillation mode * FsX'tal=32.768kHz by crystal oscillation mode * System clock set to 15MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(3) * FmCF=0Hz(oscillation stopped) * FsX'tal=32.768kHz by crystal oscillation mode IDDOP(4) * System clock set to internal RC oscillation * frequency variable RC oscillation stopped *1/2 frequency division ratio. IDDOP(5) * FmCF=0Hz(oscillation stopped) * FsX'tal=32.768kHz by crystal oscillation mode. IDDOP(6) * System clock set to 1MHz with frequency variable RC oscillation * Internal RC oscillation stopped * 1/2 frequency division ratio. IDDOP(7) * FmCF=0Hz(oscillation stopped) * FsX'tal=32.768kHz by crystal oscillation mode. IDDOP(8) * System clock set to 32.768kHz side. * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/2 frequency division ratio. 2.7 to 4.5 18 80 A 4.5 to 5.5 40 120 2.7 to 4.5 0.8 4.5 4.5 to 5.5 1.3 6 2.7 to 4.5 0.4 3 4.5 to 5.5 0.7 4.5 4.5 to 5.5 10 24 mA 4.75 to 5.25 17 38 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors Continued on next page. No.A0432-21/32 LC87F06J2A Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 =VDDVCO =VDDODA * HALT mode * FmCF=15MHz ceramic oscillation mode * FsX'tal=32.768kHz by crystal oscillation mode * System clock set to 15MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDHALT(2) * HALT mode * FmCF=0Hz(oscillation stopped) * FsX'tal=32.768kHz by crystal IDDHALT(3) oscillation mode * System clock set to internal RC oscillation * frequency variable RC oscillation stopped *1/2 frequency division ratio. IDDHALT(4) * HALT mode * FmCF=0Hz(oscillation stopped) * FsX'tal=32.768kHz by crystal oscillation mode. IDDHALT(5) * System clock set to 1MHz with frequency variable RC oscillation * Internal RC oscillation stopped * 1/2 frequency division ratio. IDDHALT(6) * HALT mode * FmCF=0Hz(oscillation stopped) * FsX'tal=32.768kHz by crystal oscillation mode. IDDHALT(7) * System clock set to 32.768kHz side. * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/2 frequency division ratio. Current drain during HOLD mode Current drain during timebase clock HOLD mode IDDHOLD(4) IDDHOLD(2) IDDHOLD(3) VDD1 IDDHOLD(1) VDD1 * HOLD mode * CF1=VDD or open (External clock mode) 2.7 to 4.5 * Timer HOLD mode * CF1=VDD or open (External clock mode) * FsX'tal=32.768kHz by crystal oscillation mode 4.5 to 5.5 2.7 to 4.5 0.02 21 7 15 60 40 4.5 to 5.5 0.085 20 2.7 to 4.5 10 50 A 4.5 to 5.5 25 70 2.7 to 4.5 0.6 3.5 4.5 to 5.5 1.0 4.5 2.7 to 4.5 0.2 1 mA 4.5 to 5.5 0.4 1.5 4.5 to 5.5 5 10 Conditions VDD[V] min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors F-ROM Write Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter Onboard programming current Programming time tFW(1) * 128-byte programming * Erasing current including * Time for setting up 128 byte data is excluded. 4.5 to 5.5 25 35 ms Symbol IDDFW(1) Pins/ Remarks VDD1 Conditions VDD[V] * 128-byte programming * Erasing current including 4.5 to 5.5 25 40 mA min Specification typ max unit No.A0432-22/32 LC87F06J2A UART(Full Duplex) Operating Conditions at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter Clock rate Symbol UBR,UBR2 Pins/Remarks UTX1(P32), URX1(P33), UTX2(P34), URX2(P35) 2.7 to 5.5 16/3 8192/3 tCYC Conditions VDD[V] min Specification typ max unit Data length: 7,8,and 9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: Non Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H) Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission UBR, UBR2 Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H) Stop bit Received data (LSB first) End of reception Start bit Start of reception UBR, UBR2 No.A0432-23/32 LC87F06J2A Automatic transmission output characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V Parameter Frequency Low level pulse width tSCKLA(9) High level pulse width tSCKHA(9) tBLKSEP(9a) See fig. 8. * Transfer continuous data blocks * (Note10-1) tBLKSEP(9b) See fig. 8. * Transfer continuous data blocks with skipping S-number of data blocks * (Note10-1) Frequency Output clock Low level pulse width High level pulse width Output delay Serial output time tSCK(10) tSCKL(10) tSCKLA(10) tSCKH(10) tSCKHA(10) tdDO(8) SB7(PA1) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output mode. * See fig. 8. 4.5 to 5.5 1tCYC +0.05 s SCK7(PA2), * CMOS output selected * See fig. 8. * (Note10-1) 4.5 to 5.5 26/3 1/2 1/2 1/2 1.5 tSCK 4+ (2/3) *S 4 tSCKH(9) 4.5 to 5.5 Symbol tSCK(9) tSCKL(9) Pins/ Remarks SCK7(PA2), See fig. 8. * (Note10-1) Conditions VDD[V] min 4 2 2 2 2 tCYC Specification typ max unit Note10-1: When starting transmission, a time from ECST begin set when serial clock is "H" to the first negative edge of serial clock must be longer than the following. (4 + (2/3) * S) * tCYC S: Skipping number of data block when starting transmission. Serial clock Input clock No.A0432-24/32 LC87F06J2A VDD1, VSS1 Terminal condition It is necessary to place capacitors between VDD1 and VSS1 as describe below. * Place capacitors as close to VDD1 and VSS1 as possible. * Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1', L2 = L2'). * Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel. * Capacitance of C2 must be more than 0.05F. * Use thicker pattern for VDD1 and VSS1. L2 L1 VSS1 C1 C2 VDD1 L1' L2' VDDVCO, VSSVCO Terminal condition It is necessary to place capacitors between VDDVCO and VSSVCO as describe below. * Place capacitors as close to VDDVCO and VSSVCO as possible. * Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L3 = L3', L4 = L4'). * Place high capacitance capacitor C3 and low capacitance capacitor C4 in parallel. * Capacitance of C4 must be more than 0.05F. * Use thicker pattern for VDDVCO and VSSVCO. L3 L4 VSSVCO C3 C4 VDDVCO L4' L3' No.A0432-25/32 LC87F06J2A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 15MHz MURATA CSTCE15M0V53-R0 (15) C2 [pF] (15) Rd1 [] 470 Operating Voltage Range [V] 3.0 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 max [ms] 0.5 Internal C1, C2 SMD-type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in follwing cases (see Figure 4). * The time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit. * The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock oscillation circuit is executed. * The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and ocsillation is started. * The time interval that is required for the oscillation to get stabilized after the X'tal Hold mode, under the state which the CFSTOP (bit 0 of the OCR register) = 0, is reset and ocsillation is started. Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name Oscillator Name C3 [pF] 32.768kHz EPSON TOYOCOM MC-306 18 Circuit Constant C4 [pF] 18 Rf1 [] OPEN Rd2 [] 560k Operating Voltage Range [V] 2.2 to 5.5 Oscillation Stabilization Time typ [s] 1.3 max [s] Applicable 3.0 CL value = 12.5pF SMD-type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in follwing cases (see Figure 4). * The time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit. * The time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed. * The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the EXTOSC (bit 6 of the OCR register) = 1, is reset and ocsillation is started. * The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the DMSRUN (bit 7 of the DMSCNT register) = 1, is reset and ocsillation is started. No.A0432-26/32 LC87F06J2A Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 Rd1 XT1 XT2 Rf1 Rd2 C1 CF C2 C3 X'tal C4 Figure 1 Ceramic Oscillation Circuit Figure 2 Crystal Oscillation Circuit 0.5VDD Figure 3 AC Timing Point No.A0432-27/32 LC87F06J2A VDD Power Supply VDD limit GND Reset time RES Internal RC Resonator tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operating mode Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilization Time HOLD release signal HOLD release signal VALID Internal RC Resonator tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operation mode HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A0432-28/32 LC87F06J2A VDD RRES RES CRES Note : Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage. Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (only SIO0,2) Continuous trans/rec interval (only SIO7,8) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH Data RAM transmission period (only SIO0,2) Continuous trans/rec interval (only SIO7,8) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Condition No.A0432-29/32 LC87F06J2A SIOCLK: DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 tSCK tSCKL SIOCLK: tdDO DATAOUT: tSCKH tSCKLA SIOCLK: tdDO DATAOUT: tSCKHA SIOCLK: DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Transmission interval over blocks DO8 tSCKLA SIOCLK: tdDO DATAOUT: tBLKSEP Figure 8 Automatic Transmission Output Waveforms No.A0432-30/32 LC87F06J2A Table 3 Cfcvd constants Cfcvd VPS/PDC/PAL-WSS Antiope EPG-J VBID XDS-1X XDS-2X 820pF OPEN Composite Video Signal 1F C-Video Video Buffer 220 PB6/CVD/CSYNC Cfcvd Figure 9 Recommended CVD Circuit 1k PB4/FILTSLC + 2.2F Cfs VSSVCO Cfs=OPEN Figure 10 Recommended FILTSLC Circuit No.A0432-31/32 LC87F06J2A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.A0432-32/32 |
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